Design and test of a sub -45 nm non-aligned double gate inverter in TCAD environment: static and dynamic analysis
Author:
Affiliation:
1. School of Electronics Engineering, VIT-AP University, Vijayawada, Guntur, India
Publisher
Informa UK Limited
Link
https://www.tandfonline.com/doi/pdf/10.1080/21681724.2024.2372735
Reference19 articles.
1. Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study
2. Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models
3. Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications
4. A Novel Approach to Investigate Analog and Digital Circuit Applications of Silicon Junctionless-Double-Gate (JL-DG) MOSFETs
5. Review of the Nanoscale FinFET Device for the Applications in Nano-regime
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