Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications-Reference-Cited by-同舟云学术

Extraction of performance parameters of nanoscale SOI LDD-FinFET using a semi-analytical model of capacitance and channel potential for low-power applications

Published:2020-09-12 Issue:10 Volume:126 Page:
ISSN:0947-8396
Container-title:Applied Physics A
language:en
Short-container-title:Appl. Phys. A

Author:

Dixit Ankit,Samajdar Dip Prakash^ORCID

Publisher

Springer Science and Business Media LLC

Subject

General Materials Science,General Chemistry

Link

https://link.springer.com/content/pdf/10.1007/s00339-020-03970-z.pdf

Reference46 articles.

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3. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.J. King, et al. FinFET scaling to 10 nm gate length. In Digest. International Electron Devices Meeting, IEEE (2002), pp. 251–254. https://doi.org/10.1109/IEDM.2002.1175825

4. Y. Taur, C.H. Wann, D.J. Frank, 25 nm CMOS design considerations. In International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217). IEEE (1998), pp. 789–792. https://doi.org/10.1109/IEDM.1998.746474

5. H. Zhu, H. Zhong, T. Kawamura, Q. Liang, E. Leobandung, S.F. Huang, On the control of short-channel effect for MOSFETs with reverse halo implantation. IEEE Electron. Dev. Lett. 28(2), 168–170 (2007). https://doi.org/10.1109/LED.2006.889230

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