High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell-Reference-Cited by-同舟云学术

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High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

Published:2014-03-25 Issue:1 Volume:78 Page:57-68
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Sharma Vijay Kumar,Patel Sumit,Pattanaik Manisha

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://link.springer.com/content/pdf/10.1007/s11277-014-1735-x.pdf

Reference12 articles.

1. Sharma, V. K., & Pattanaik, M. (2013). VLSI scaling methods and low power CMOS buffer circuit. Journal of Semiconductors, 34, 095001.

2. Sharma, V. K., Pattanaik, M., & Raj, B. (2014). ONOFIC approach: Low power high speed nanoscale VLSI circuits design. International Journal of Electronics, 101, 61–73.

3. Sharma, V. K., Pattanaik, M., & Raj, B. (2014). PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectronics Reliability, 54, 90–99.

4. Seevinck, E., List, F., & Lohstroh, J. (1987). Static-noise margin analysis of MOS SRAM cells. IEEE Journal of Solid-State Circuits, 22, 748–754.

5. Zhai, B., Hanson, S., Blaauw, D., & Sylvester, D. (2008). A variation-tolerant sub-200 mv 6T subthreshold SRAM. IEEE Journal of Solid-State Circuits, 43, 2338–2348.

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