Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies-Reference-Cited by-同舟云学术

Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies

Published:2023-05-03 Issue: Volume: Page:1-14
ISSN:0377-2063
Container-title:IETE Journal of Research
language:en
Short-container-title:IETE Journal of Research

Author:

Sharma Divya¹,Rai Amrita²,Debbarma Sunita³,Prakash Om⁴,Ojha Mukesh Kumar⁵,Nath Vijay¹^ORCID

Affiliation:

1. Department of Electronics & Communications Engineering, Birla Institute of Technology, VLSI Design Lab, Mesra, Ranchi, Jharkhand 835215, India

2. Department of Electronics and Communication Engineering, GL Bajaj Institute of Technology and Management, Greater Noida, Uttar Pradesh 201307, India

3. Department of Electronics & Communications Engineering, National Institute of Technology, Silchar, Assam 788010, India

4. Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering and Technology, Chittoor, Andhra Pradesh 517127, India

5. Department of Electronics and Communication Engineering, GNIOT Group of Institution, Greater Noida, Uttar Pradesh 201306, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Science Applications,Theoretical Computer Science

Link

https://www.tandfonline.com/doi/pdf/10.1080/03772063.2023.2204857

Reference40 articles.

1. Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing

2. Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

3. Improved Noise Margin and Reduced Power Consumption in Subthreshold Adiabatic Logic Using Dual Rail Power Supply

4. Analysis of Sub-Threshold Adiabatic Logic Model Using Junctionless MOSFET for Low Power Application

5. VLSI implementation of ultra power optimized adiabatic logic based full adder cell

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