Design and analysis of a logic model for ultra‐low power near threshold adiabatic computing
Author:
Affiliation:
1. Department of Electronics and Communication EngineeringMeghnad Saha Institute of TechnologyKolkata700150India
2. Department of Electronics and Telecommunication EngineeringJadavpur UniversityKolkata700032India
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering,Control and Systems Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0386
Reference28 articles.
1. Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis
2. Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation
3. Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS
4. Ultralow-Power Design in Near-Threshold Region
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