Variation aware intuitive clock gating to mitigate on-chip power supply noise-Reference-Cited by-同舟云学术

Variation aware intuitive clock gating to mitigate on-chip power supply noise

Published:2018-04-11 Issue:9 Volume:105 Page:1487-1500
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Majumder Alak¹^ORCID,Bhattacharjee Pritam¹^ORCID

Affiliation:

1. Integrated Circuit & System (i-CAS) Lab, Department of Electronics & Communication Engineering, National Institute of Technology, Yupia, Arunachal Pradesh, India

Funder

Ministry of Electronics and Information technology

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2018.1460873

Reference20 articles.

1. Method to Simulate Rise Time of Current Drawn by a Microprocessor

2. Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips

3. Clock Jitter Reduction and Flat Frequency Generation in PLL Using Autogenerated Control Feedback

4. Branson, C. N. (1989).U.S. Patent No. 4,819,164. Washington, DC: U.S. Patent and Trademark Office.

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