Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC-Reference-Cited by-同舟云学术

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Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC

Published:2021 Issue: Volume: Page:1-1
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Bhattacharjee Pritam,Rana Prerna,Bhattacharyya Bidyut K.,Majumder Alak

Funder

Ministry of Electronics and Information technology

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx7/43/6917053/09493723.pdf?arnumber=9493723

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS;2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA);2023-04-19

2. On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies;International Journal of Electronics;2022-12-28

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