Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS
Author:
Affiliation:
1. Amrita Vishwa Vidyapeetham,Amrita School of Engineering,Department of ECE,Kerala,India,690525
2. National Institute of Technology,iCAS Laboratory,Department of ECE,Arunachal Pradesh,India,791113
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10109000/10109002/10109063.pdf?arnumber=10109063
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4. 45-year CPU evolution: one law and two equations;etiemble;arXiv preprint arXiv 1803 00254,2018
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