A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/8911/28180/01260929.pdf?arnumber=1260929
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Design and Development of Low Power and Area Efficient Design for VLSI Circuits;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20
2. Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS;2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA);2023-04-19
3. Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology;Applied Sciences;2023-03-08
4. A Literature Review: Different Leakage Reduction Techniques for CMOS circuits;2021 International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA);2021-10-08
5. Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing;Facta universitatis - series: Electronics and Energetics;2021
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