A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors-Reference-Cited by-同舟云学术

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A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors

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Container-title:17th International Conference on VLSI Design. Proceedings.
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Author:

Hanchate N.,Ranganathan N.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/8911/28180/01260929.pdf?arnumber=1260929

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficient Integration of Ultra-low Power Techniques and Energy Harvesting in Self-Sufficient Devices: A Comprehensive Overview of Current Progress and Future Directions;Sensors;2024-07-10

2. Design and Development of Low Power and Area Efficient Design for VLSI Circuits;2023 4th International Conference on Smart Electronics and Communication (ICOSEC);2023-09-20

3. Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS;2023 33rd International Conference Radioelektronika (RADIOELEKTRONIKA);2023-04-19

4. Triple-Threshold Path-Based Static Power-Optimization Methodology (TPSPOM) for Designing SOC Applications Using 28 nm MTCMOS Technology;Applied Sciences;2023-03-08

5. A Literature Review: Different Leakage Reduction Techniques for CMOS circuits;2021 International Conference on Advancements in Electrical, Electronics, Communication, Computing and Automation (ICAECA);2021-10-08

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