10T FinFET based SRAM cell with improved stability for low power applications
Author:
Affiliation:
1. Electronics and Communication, Manipal University Jaipur, Jaipur, India
Publisher
Informa UK Limited
Subject
Electrical and Electronic Engineering
Link
https://www.tandfonline.com/doi/pdf/10.1080/00207217.2021.2001868
Reference28 articles.
1. Analysis of 6 T SRAM cell in sub-45 nm CMOS and FinFET technologies
2. A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies
3. Reliable and high performance asymmetric FinFET SRAM cell using back-gate control
4. Thermal modeling and analysis of 3D multi-processor chips
5. Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing
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