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RES eliminated fault detection

Published:2017-02-10 Issue:1 Volume:6 Page:14-22
ISSN:2168-1724
Container-title:International Journal of Electronics Letters
language:en
Short-container-title:International Journal of Electronics Letters

Author:

Takher Vikram Singh¹,Choudhary Rahul Raj²

Affiliation:

1. Department of Electronics Engineering, Government Polytechnic College, Bikaner, India and Scholar, Vivekanand Global University, Jaipur, Rajasthan, India

2. Department of Electronic Instrumentation and Control Engineering, Government Engineering College Bikaner, Bikaner, Rajasthan, India

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Instrumentation,Electronic, Optical and Magnetic Materials

Link

https://www.tandfonline.com/doi/pdf/10.1080/21681724.2017.1285432

Reference11 articles.

1. Scheduling tests for VLSI systems under power constraints

2. Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories

3. Minimizing Test Power in SRAM through Reduction of Pre-charge Activity

4. Reducing Power Dissipation in SRAM during Test

5. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low power test architecture for dynamic read destructive fault detection in SRAM;International Journal of Electronics;2018-01-15

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