Author:
Chou R.M.,Saluja K.K.,Agrawal V.D.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
140 articles.
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1. Concurrent Low Power Built-in Self-Test for Safety Critical SoCs;2024 IEEE 8th International Test Conference India (ITC India);2024-07-21
2. On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06
3. Power-aware partitioning and test time reduction for 3D-SoC;Innovations in Systems and Software Engineering;2022-09-06
4. Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-11
5. Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *;2020 IEEE 29th Asian Test Symposium (ATS);2020-11-23