Low Power Implementation of 32-Bit RISC Processor with Pipelining
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-10-8234-4_27
Reference11 articles.
1. N. Joseph, Sabarinath, et al, “FPGA based implementation of high performance architectural level low power 32-bit RISC core”, International conference on advances in recent technologies in communication and computing, Annual IEEE, pp. 53–57, 2009.
2. Shofiqul, Debanjan, et al, “Design of high speed pipelined execution unit of 32-bit RISC processor”, Annual IEEE, pp. 1–5, 2006.
3. Roopa Kulkarni, S.Y. Kulkarni, “Power analysis and comparison of clock gated techniques implemented on a 16-bit ALU”, Proceedings of International conference on circuits, communication, control and computing, pp. 416–420, November 2014.
4. Roopa Kulkarni, S.Y. Kulkarni, “Energy efficient implementation of 16-bit ALU using block enabled clock gating technique”, Annual IEEE India conference (INDICON), 2014.
5. Aneesh Raveendran, Vinayak Baramu Patil, David Selvakumar, Vivian Desalphine, “A RISC-V Instruction Set Processor-Micro architecture Design and Analysis”, International conference on VLSI system, Architectures, Technology and Application (VLSI-SATA), 2016 IEEE.
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