A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation-Reference-Cited by-同舟云学术

A Survey on In-Order 5-Stage Pipeline RISC-V Processor Implementation

Published:2022-06-10 Issue: Volume: Page:777-784
ISSN:2367-3370
Container-title:Information and Communication Technology for Competitive Strategies (ICTCS 2021)
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Author:

Mallidu Jayashree,Siddamal Saroja V.^ORCID

Publisher

Springer Nature Singapore

Link

https://link.springer.com/content/pdf/10.1007/978-981-19-0098-3_73

Reference7 articles.

1. Khimchenko I, Christian K, Peter S (2019) RISC-V processor with configurable pipeline stage placement. In: Dortmund international research conference

2. Patsidis K et al (2018) A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension. Microprocess Microsyst 61:1–10

3. Gao, LX, Zha HS (2013) Pipelined RISC processor design and FPGA implementation. Appl Mech Mater 336

4. Olanrewaju RF et al (2017) Design and Implementation of a five stage pipelining architecture simulator for RiSC-16 instruction set. Indian J Sci Technol 10(3):1–9

5. Mangalwedhe S, Roopa K, Kulkarni SY (2019) Low power implementation of 32-bit RISC processor with pipelining. In: Proceeding of the second international conference on Microelectronics, Computing & Communication Systems (MCCS 2017). Springer, Singapore

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