A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension-Reference-Cited by-同舟云学术

A low-cost synthesizable RISC-V dual-issue processor core leveraging the compressed Instruction Set Extension

Author:

Patsidis Karyofyllis^ORCID,Konstantinou Dimitris,Nicopoulos Chrysostomos,Dimitrakopoulos Giorgos^ORCID

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference32 articles.

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