HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems
Author:
Affiliation:
1. Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
Funder
Israel Innovation Authority through the GenPro Magnet Program
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10391078/10289711.pdf?arnumber=10289711
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-09
2. Exploring RISC-V Based DNN Accelerators;2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS);2024-07-29
3. Integration and Verification of L1 Data Cache in SweRV EH1;2024 International Conference on Engineering & Computing Technologies (ICECT);2024-05-23
4. Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
5. Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode;IEEE Transactions on Computers;2024-02
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