Optimization of ALU with gated clock and its internal modules in RVIM64 processor

Abstract

Abstract Low power consumption and area are the main research directions of the RISC-V architecture processor, and the arithmetic logic operation unit (ALU) is the key part that affects the overall performance of the processor. In order to improve the performance of the RISC-V architecture processor, we adopted the strategy of reducing the overall power consumption and area of ALU, by using the method of adding a gated clock circuit and optimizing the structure of the comparison module and shift module in ALU. Under the conditions of 90 nm technology, the temperature and the voltage were set to 125 °C and 1 V respectively. The synthesis results of ALU are as follows: the area is 111061 um2, the power consumption is 20.58 MW, and the delay is 20.58 ps. Compared with other traditional ALU, the area is reduced by 46%, and power consumption is reduced by about 48%.