Abstract
Abstract
In embedded IoT applications, in order to meet the needs of small area, low power consumption, and high performance, this paper designs a 32-bit low-power, high-performance microprocessor based on the RISC-V instruction set architecture. It uses a 3-stage pipeline structure with static branch prediction function, supports RV32IM instruction set, and adopts AHB bus as the control bus. The logic function of the processor was verified under the iverilog environment, and the simulation results showed that the processor can run normally. The CoreMark score of 2.38 CoreMark/MHz was measured by running the CoreMark running program, and it supports FreeRTOS transplantation. The analysis and verification results show that the design can be well applied to small-area, low-power embedded application scenarios.
Subject
General Physics and Astronomy
Reference7 articles.
1. Research and performance optimization of five-stage pipeline RISC-V processor[J/OL];Jiemin;Microelectronics and Computer
2. A RISC-V instruction set processor-micro-architecture design and anal ysis[C]//2016 International Conference on VLSI Systems;Raveendran,2016
3. Scratchpad memory; design alternative for cache on-chip memory inembedded systems[C];Banakar,2002
4. RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nmFD-SOI[J];Keller;IEEE Journal of Solid-State Circuits,2017
5. Out of order floating point coprocessor for RISC V ISA[C];Patil,2015
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献