Custom Design of 16 Bit RISC Processor Using Low Power Pipelining-Reference-Cited by-同舟云学术

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Custom Design of 16 Bit RISC Processor Using Low Power Pipelining

Published:2024-06-21 Issue: Volume:2 Page:1-6
ISSN:
Container-title:2023 4th International Conference on Intelligent Technologies (CONIT)
language:
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Author:

Gangandhar K G¹,Indhushree D¹,Krishnakumar G¹,Shwetha M P¹

Affiliation:

1. Dayananda Sagar University,Electronics and Communication,Bengaluru,Karnataka

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10625770/10625923/10627227.pdf?arnumber=10627227

Reference9 articles.

1. Design & analysis of 16 bit RISC processor using low power pipelining

2. ASIC design of MIPS based RISC processor for high performance

3. An Optimum Design and Implementation of a 16-bit ALU on CADENCE Using RISC-V Architecture

4. An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors

5. Design and Analysis of High Speed RISC Processor Using Pipelining Technique

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