1. Custom Design of 16 Bit RISC Processor Using Low Power Pipelining;2023 4th International Conference on Intelligent Technologies (CONIT);2024-06-21
2. ASIC Design of High-Performance MIPS Processor Using Aprisa;Lecture Notes in Electrical Engineering;2024
3. Design of RISCV processor using verilog;i-manager's Journal on Digital Signal Processing;2024
4. Five-Stage Pipelined MIPS Processor Verification Driver Module using UVM;2023 International Conference on Sustainable Computing and Smart Systems (ICSCSS);2023-06-14
5. Design and Analysis of a Multi Clocked Pipelined Processor Based on RISC-V;2022 International Conference on Communication, Computing and Internet of Things (IC3IoT);2022-03-10