ASIC Design of High-Performance MIPS Processor Using Aprisa
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-7077-3_44
Reference10 articles.
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2. Ashok A, Ravi V (2017) ASIC design of MIPS based RISC processor for high performance. In: 2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), Chennai, India, pp 263–269. https://doi.org/10.1109/ICNETS2.2017.8067945
3. Bharadwaja KR, Teja MN, Neelima K et al (2015) Advanced low power RISC processor design using MIPS instruction set. In: 2015 2nd International Conference on Electronics and Communication Systems (ICECS), Coimbatore, India, pp 1252–1258. https://doi.org/10.1109/ECS.2015.7124785
4. Dewangan GK, Prasad G, Mandi BC (2021) Design and implementation of 32 bit MIPS based RISC processor. In: 2021 8th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, pp 998–1002. https://doi.org/10.1109/SPIN52536.2021.9566007
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