High Speed and Low Power Buffer Based Parallel Multiplier for Computer Arithmetic
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-7345-3_34
Reference19 articles.
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3. Tabei SM, Nikmehr H (2017) An unsigned truncated sequential multiplier with variable error compensation. Microprocessors Microsyst 49:9–17
4. Malek S, Abdallah S, Chehab A, Elhajj IH, Kayssi A (2017) Low-Power and high-speed shift-based multiplier for error tolerant applications. Microprocess Microsyst 52:566–574
5. Paliwal P, Sharma JB, Nath V (2019) Comparative study of FFA architectures using different multiplier and adder topologies. MicrosystTechnol 1–8
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