Low-power and high-speed shift-based multiplier for error tolerant applications-Reference-Cited by-同舟云学术

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Low-power and high-speed shift-based multiplier for error tolerant applications

Published:2017-07 Issue: Volume:52 Page:566-574
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Malek Sami,Abdallah Sarah,Chehab Ali,Elhajj Imad H.,Kayssi Ayman

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference8 articles.

1. Stochastic hardware architectures: a survey;Abdallah,2012

2. Characterization of error-tolerant applications when protecting control data;Thaker,2006

3. BZ-FAD: a low-power low-area multiplier based on shift-and-add architecture;Mottaghi-Dastjerdi;IEEE Trans. Very Large Scale Integr. Circuits,2009

4. An enhanced carry elimination adder for low power VLSI applications;Muralidharan;Int. J. Eng. Res. Appl. (IJERA),2012

5. Low-power high-speed multiplier for error-tolerant application;Kyaw,2010

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach;Circuits, Systems, and Signal Processing;2021-03-18

2. High Speed and Low Power Buffer Based Parallel Multiplier for Computer Arithmetic;Lecture Notes in Networks and Systems;2020-09-25

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