Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach-Reference-Cited by-同舟云学术

Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

Published:2021-03-18 Issue:9 Volume:40 Page:4407-4427
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Solanki Vaibhavi,Darji A. D.,Singapuri Harikrishna^ORCID

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s00034-021-01671-3.pdf

Reference27 articles.

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2. S. Asif, Y. Kong, Performance analysis of wallace and radix-4 booth-wallace multipliers. In Proceedings of the 2015 Electronic System Level Synthesis Conference (ESLsyn), pp 17–22 (2015)

3. S. Asif, Y. Kong, Analysis of different architectures of counter based wallace multipliers. In Proceedings of the 2015 Tenth International Conference on Computer Engineering Systems (ICCES), pp 139–144, (2015). https://doi.org/10.1109/ICCES.2015.7393034

4. S. Asif, Y. Kong, Design of an algorithmic wallace multiplier using high speed counters. In Proceedings of the 2015 Tenth International Conference on Computer Engineering Systems (ICCES), pp 133–138 (2015). https://doi.org/10.1109/ICCES.2015.7393033

5. C. Chang, J. Gu, M. Zhang, Ultra low-voltage low-power cmos 4–2 and 5–2 compressors for fast arithmetic circuits. IEEE Trans. Circ. Syst. I Reg. Papers 51(10), 1985–1997 (2004). https://doi.org/10.1109/TCSI.2004.835683

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