High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system-Reference-Cited by-同舟云学术

High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system

Published:2023-11 Issue: Volume:93 Page:102055
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Ponraj Jeyakumar,Jeyabharath R.,Veena P.,Srihari Tharumar

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference39 articles.

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5. An efficient VLSI architecture for fast motion estimation exploiting zero motion prejudgment technique and a new quadrant-based search algorithm in HEVC;Shajin;Circ. Syst. Signal Process.,2022

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