Comparative study of FFA architectures using different multiplier and adder topologies

Author:

Paliwal Payal,Sharma Janki Ballabh,Nath Vijay

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. Acha JI (1989) Computational structures for fast implementation of L-path and L-block digital filters. IEEE Trans Circuits Syst 36(6):805–812

2. Antoniou A (1993) Digital filter: analysis, design and applications. McGraw-Hill, New York

3. Chandra A, Chattopadhyay S (2015) Design of hardware efficient FIR filter: a review of the state of the art approaches. Int J 19:212–226

4. Chung JG, Parhi KK (2002) Frequency-spectrum-based low-area low-power parallel FIR filter design. EURASIP J Appl Signal Process 2002(9):444–453

5. Gupta T, Sharma JB (2018) Han-Carlson adder based high-speed vedic multiplier for complex multiplication. Microsyst Technol 24:3901–3906 (ISSN 0946-7076)

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