Design and Analysis of 16-bit Vedic Multiplier Using UT Sutra of Vedic Mathematics-Reference-Cited by-同舟云学术

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Design and Analysis of 16-bit Vedic Multiplier Using UT Sutra of Vedic Mathematics

Published:2023-03-14 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Innovative Data Communication Technologies and Application (ICIDCA)
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Author:

P Bini Palas¹,R Priya Dharshni¹,S Rashida Tayiba¹

Affiliation:

1. Easwari Engineering College,Electronics and Communication Engineering,Chennai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10099475/10099489/10099599.pdf?arnumber=10099599

Reference15 articles.

1. VHDL Implementation of Floating Point Multiplier Based on Vedic Multiplication Technique;sachan;International Journal of Science Engineering and Technology,2015

2. Design of Floating Point Vedic Multiplier using VHDL;singh;International Journal of Research and Development in Applied Science and Engineering (IJRDASE),2016

3. Design of Vedic multiplier using Urdhva Tiryagbhyam Sutra;harsha;International Journal of Advance Research Ideas and Innovations in Technology,2019

4. Memory Based Floating Point FFT Processor Using Vedic Multiplication for Pulse Doppler RADAR

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 16-bit Vedic multiplier Using Carry Skip Adder;2024 International Conference on Intelligent Systems for Cybersecurity (ISCS);2024-05-03

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