Author:
Venkata Dharani B.,Joseph Sneha M.,Kumar Sanjeev,Nandan Durgesh
Reference23 articles.
1. Govekar D, Amonkar A (2017) Design and implementation of high speed modified booth multiplier using hybrid adder. In: International conference on computing methodologies and communication (ICCMC), 18–19 July 2017, pp 138–143
2. Chen Y-H, Chang T-Y, Jou R-Y (2010) A statistical error-compensated booth multipliers and its DCT applications. In: TENCON 2010 - 2010 IEEE region 10 conference, 21–24 November 2010, pp 1146–1149
3. Prabhu AS, Elakya V (2012) Design of modified low power booth multiplier. In: 2012 international conference on computing, communication and applications, 22–24 February 2012, pp 1–6
4. Nandan D, Kanungo J, Mahajan A (2017) An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition. Integration 58:134–141.
https://doi.org/10.1016/j.vlsi.2017.02.003
5. Nandan D, Kanungo J, Mahajan A (2018) An errorless Gaussian filter for image processing by using expanded operand decomposition logarithm multiplication. J Ambient Intell Humaniz Comput.
https://doi.org/10.1007/s12652018-0933-x
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