An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition-Reference-Cited by-同舟云学术

An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition

Published:2017-06 Issue: Volume:58 Page:134-141
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Durgesh Nandan ,Kanungo Jitendra,Mahajan Anurag

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference30 articles.

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5. Low-power logarithmic number system addition / subtraction and their impact on digital filters;Kouretas;IEEE Trans. Comput.,2013

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