Floating Point Multipliers Based On Vedic Mathematics
Author:
Affiliation:
1. BMS Institute of Technology and Management,Department of Electronics and Communication Engineering,Bengaluru,Karnataka,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10275783/10275784/10275996.pdf?arnumber=10275996
Reference16 articles.
1. What every computer scientist should know about floating-point arithmetic
2. An Automatable Formal Semantics for IEEE-754 Floating-Point Arithmetic
3. Implementation of 32-Bit Complex Floating-Point Multiplier Using Vedic Multiplier, Array Multiplier, and Combined integer and floating-point Multiplier (CIFM);rahul;2020 IEEE International Conference for Innovation in Technology (INOCON),0
4. A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
5. Applications of Vedic multiplier - A Review
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