Author:
Govekar Divya,Amonkar Ameeta
Cited by
12 articles.
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1. High efficient accurate DL-PO logic multiplier design for low power applications;AIP Conference Proceedings;2024
2. Design and Analysis of Multipliers using Hybrid Full Adder;2023 7th International Conference on Electronics, Communication and Aerospace Technology (ICECA);2023-11-22
3. FPGA Implementation of ECG Denoising using Kaiser Window Technique;2023 3rd International Conference on Pervasive Computing and Social Networking (ICPCSN);2023-06
4. Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing;2023 4th International Conference for Emerging Technology (INCET);2023-05-26
5. FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU;2023 International Conference on Control, Communication and Computing (ICCC);2023-05-19