Author:
Ishak M. H. H.,Abdullah M. Z.,Aziz M. S. Abdul,Saad A. A.,Abdullah M. K.,Loh W. K.,Ooi R. C.,Ooi C. K.
Publisher
Springer Science and Business Media LLC
Reference20 articles.
1. Hon, R.; Lee, S.W.R.; Zhang, S.X.; Wong, C.K.: Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection. 2005 7th Electron. Packag. Technol. Conf. 2, 384–389 (2005)
2. Farooq, M.; Iyer, S.: 3D integration review. Sci. China Inf. Sci. 54, 1012–1025 (2011)
3. Davis, W.R.; Wilson, J.; Mick, S.; Xu, J.; Hua, H.; Mineo, C.; Sule, A.M.; Steer, M.; Franzon, P.D.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22, 498–510 (2005)
4. Abdullah, M.K.; Abdullah, M.Z.; Kamarudin, S.; Ariff, Z.M.: Study of flow visualization in stacked-chip scale packages (S-CSP). Int. Commun. Heat Mass Transf. 34, 820–828 (2007)
5. Bae, D.H.; Lee, M.C.; Lee, E.S.; Yun, H.C.; Lim, J.C.; Kim, I.B.: Simulation of encapsulation process for BGA type semi-conducting microchip. IEEE Trans. Compo. Packag. Technol. 27, 200–209 (2003)
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