Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection-Reference-Cited by-同舟云学术

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Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection

Published: Issue: Volume: Page:
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Container-title:2005 7th Electronic Packaging Technology Conference
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Author:

Hon R.,Lee S.W.R.,Zhang S.X.,Wong C.K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/10751/33892/01614434.pdf?arnumber=1614434

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Study on copper protrusion of through-silicon via in a 3-D integrated circuit;Materials Science and Engineering: A;2019-05

2. Study on the Fluid–Structure Interaction at Different Layout of Stacked Chip in Molded Packaging;Arabian Journal for Science and Engineering;2017-06-15

3. Characterization of Copper Diffusion in Through Silicon Vias;Materials for Advanced Packaging;2016-11-19

4. Fabrication and shear strength analysis of Sn-3.5Ag/Cu-filled TSV for 3D microelectronic packaging;Electronic Materials Letters;2016-09-09

5. Experimental assessment of on-chip liquid cooling through microchannels with de-ionized water and diluted ethylene glycol;Japanese Journal of Applied Physics;2016-05-20

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