Author:
Zhu Zhangming,Xiao Yu,Xu Lifeng,Ding Haoyu,Yang Yintang
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference12 articles.
1. Min, B., et al. (2003). A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE Journal of Solid-State Circuits, 38(12), 2031–2039.
2. Shin, C.-S., & Ahn, G.-C. (2011). A 10-bit 100-MS/s dual-channel pipelined ADC using dynamic memory effect cancellation technique. IEEE Journal of Solid-State Circuits, 46(5), 274–278.
3. Wei, H., et al. (2012). An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC. IEEE Journal of Solid-State Circuits, 47(11), 2763–2772.
4. Liu, C.-C., et al., (2010). A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation. In IEEE Journal of Solid-State Circuits Conference (pp. 386–387).
5. Ginsburg, B. P., & Chandrakasan, A. P. (2007). Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 43(12), 2641–2650.
Cited by
9 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献