1. An energy-efficient hybrid SAR-VCO Δ-Σ capacitance-to-digital converter in 40-nm CMOS;Sanyal;IEEE J. Solid State Circ.,2017
2. A 14-bit 4-MS/s VCO-based SAR ADC with deep metastability facilitated mismatch calibration;Zhu;IEEE J. Solid State Circ.,2020
3. A 2.02-5.16 fJ/conversion-step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS;Chen;IEEE J. Solid State Circ.,2016
4. A 73 dB SNDR 20 MS/s 1.28 mW SAR-TDC Using Hybrid Two-step Quantization;Muhlestein,2017
5. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-range Quantizer in 45nm CMOS;Su,2019