A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor

Abstract

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.