High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock
Author:
Publisher
Springer Science and Business Media LLC
Subject
Multidisciplinary
Link
http://link.springer.com/content/pdf/10.1007/s12204-019-2065-7.pdf
Reference11 articles.
1. YUAN C, LAM Y. Low-energy and area-efficient tri-level switching scheme for SAR ADC [J]. Electronics Letters, 2012, 48(9): 482–483.
2. ZHU Z M, XIAO Y, SONG X L. V CM-based monotonic capacitor switching scheme for SAR ADC [J]. Electronics Letters, 2013, 49(5): 327–329.
3. ZHU Y, CHAN C H, CHIO U F, et al. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS [J]. IEEE Journal of Solid-State Circuits, 2010, 45(6): 1111–1121.
4. RAHIMI E, YAVARI M. Energy-efficient high-accuracy switching method for SAR ADCs [J]. Electronics Letters, 2014, 50(7): 499–501.
5. XIE L B, SU J, LIU J X, et al. Energy-efficient capacitor-splitting DAC scheme with high accuracy for SAR ADCs [J]. Electronics Letters, 2015, 51(6): 460–462.
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