Low-energy and area-efficient tri-level switching scheme for SAR ADC
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el.2011.4001?crawler=true&mimetype=application/pdf
Reference5 articles.
1. Allen, P.E., and Holberg, D.R.: ‘CMOS Analog Circuit Design’, (Oxford University Press, Inc., New York, USA 2002),2nd
2. An Energy-Efficient Charge Recycling Approach for a SAR Converter With Capacitive DAC
3. A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
4. A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
5. Merged capacitor switching based SAR ADC with highest switching energy-efficiency
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2. A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications;Micromachines;2023-12-27
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4. A 10-Bits 70-MS/s SAR ADC Based on Area-Efficient and Low- Energy Bootstrapped Switching Scheme using FIN-FET Technology;2023 International Conference on Network, Multimedia and Information Technology (NMITCON);2023-09-01
5. A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS;IEICE Electronics Express;2023-07-25
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