A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
http://link.springer.com/article/10.1007/s00034-017-0621-7/fulltext.html
Reference17 articles.
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3. D. Belot, L. Dugoujon, S. Dedieu, A 3.3 V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH. IEEE J. Solid State Circuits 33(6), 1047–1058 (1998)
4. C.-L. Chen, C.-C. Wang, C.-Y. Juan, A fast-locking clock and data recovery circuit with a lock detector loop, in Proceedings of IEEE International Symposium on Integrated Circuits, 2011, pp. 332–335
5. F.-T. Chen, J.-M. Wu, An extended phase detector 2.56/3.2Gb/s clock and data recovery design with digitally assisted lock detector, in Proceedings of IEEE International Symposium on Circuits and Systems, 2009, pp. 1831–1834
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