A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx4/4/15141/00701256.pdf?arnumber=701256
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits;Circuits, Systems, and Signal Processing;2017-08-05
2. A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-02
3. A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition;Journal of Electrical and Computer Engineering;2011
4. A 155.52 Mbps–3.125 Gbps Continuous-Rate Clock and Data Recovery Circuit;IEEE Journal of Solid-State Circuits;2006-06
5. A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit;IEEE Transactions on Circuits and Systems I: Regular Papers;2006-04
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