A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology

Author:

Ghasemian HosseinORCID,Bahrami Amin,Abiri Ebrahim,Salehi Mohammad Reza

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Comprehensive analysis of linear phase frequency detectors in phase-locked loops;AEU - International Journal of Electronics and Communications;2024-05

2. A novel replica technique based dead zone free phase frequency detector and a self-cascode current-splitting charge pump for a low-spur low power phase-locked loop architecture;AEU - International Journal of Electronics and Communications;2023-12

3. Fast Start Low Power DC-DC Conversion Circuit Design;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28

4. A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique;Circuits, Systems, and Signal Processing;2022-10-17

5. Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application;Circuits, Systems, and Signal Processing;2022-07-25

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