Comprehensive analysis of linear phase frequency detectors in phase-locked loops
Author:
Funder
VIT University
Vellore Institute of Technology, Chennai
Publisher
Elsevier BV
Reference149 articles.
1. A digitally controlled phase-locked loop with a digital phase-frequency detector for fast acquisition;Hwang;IEEE J Solid-State Circuits,2001
2. A sub-sampling-assisted phase-frequency detector for low-noise PLLs with robust operation under supply interference;Hsu;IEEE Trans Circuits Syst I Regul Pap,2015
3. Blind zone-less phase frequency detector for a low-power phase-locked loop architecture;Divya;Circuits Syst Signal Process,2023
4. A 1.0 gbps clock and data recovery circuit with two-XOR phase-frequency detector;Kim,2000
5. Hwang Y-H, Park K. Analysis of stochastic phase-frequency detector in 2x oversampling clock and data recovery, IEEE Trans Circuits Syst II: Express Briefs, http://dx.doi.org/10.1109/TCSII.2023.3335103.
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