A low-jitter leakage-free digitally calibrated phase locked loop
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering
Reference25 articles.
1. A 5.7-6.0GHz CMOS PLL with low phase noise and −68dBc reference spur;Li;Int J Electron Commun,2018
2. Fast locking technique for phase locked loop based on phase error cancellation;Karbalaei Mohammad Ali;Int J Electron Commun,2019
3. A divider-less, high speed and wide locking range phase locked loop;Erfani-Jazi;Int J Electron Commun,2015
4. Design of 0.35-ps RMS jitter 4.4–5.6-GHz frequency synthesizer with adaptive frequency calibration using 55-nm CMOS technology;Qiu;Circt Syst Signal Process,2018
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1. A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications;Journal of Circuits, Systems and Computers;2023-03-01
2. A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL Using Aperture Phase Detector-Based DLL Windowing Technique;IEEE Access;2023
3. A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme;Analog Integrated Circuits and Signal Processing;2022-05-10
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