1. H. Adrang, H. Miar-Naimi, Modeling of jitter in bang-bang CDR with Fourier series analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 60, 3–10 (2013). https://doi.org/10.1109/TCSI.2012.2215787
2. H. Adrang, H. Miar-Naimi, Nonlinear analysis of BBCDR jitter generation using Volterra series. IEEE Trans. Circuits Syst. II Express Briefs 60, 197–201 (2013). https://doi.org/10.1109/TCSII.2013.2251947
3. R.E. Best, All-Digital PLLs in Phase Locked Loops: Design, Simulation, and Applications (Oberwil, Switzerland, 2007).
4. P. Bromiley, Products and convolutions of Gaussian probability density functions. Tina-Vision Memo 3, 1–13 (2018)
5. G.P.E.V. Bueren, Clock and data recovery circuit and clock synthesizers for 40 Gb/s high-density serial I/O-links in 90-nm CMOS. Ph.D. dissertation, Dept. Elect. Eng., ETH Zurich Univ., Zürich, Switzerland (2011)