Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance-Reference-Cited by-同舟云学术

Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance

Published:2020-11-10 Issue:1 Volume:14 Page:75-86
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Basak Arighna,Sarkar Angsuman

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-020-00783-w.pdf

Reference54 articles.

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4. Mohsenifar S, Shahrokhabadi MH (2015) Gate stack high-κ materials for Si-based MOSFETs past, present, and futures. Microelectronics and Solid State Electronics 4(1):12–24

5. Datta S (2013) Recent advances in high performance CMOS transistors: from planar to non-planar. Electrochem Soc Interfac 22(1):41–46. https://doi.org/10.1149/2.F04131if

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