Optimization of Subthreshold Parameters of Graded-Channel Gate-Stack Double-Gate (GC-GS-DG) MOSFET Using PSO-CFIWA

Author:

Chowdhury Dibyendu,De Bishnu Prasad,Ghosh Sumalya,Singh Navaneet Kumar,Kar Rajib,Mandal Durbadal

Publisher

Springer Nature Singapore

Reference24 articles.

1. Basak A, Sarkar A (2020) Drain current modelling of asymmetric junctionless dual material double gate MOSFET with high K gate stack for analog and RF performance. Silicon. https://doi.org/10.1007/s12633-020-00783-w

2. Yadav VK, Rana AK (2012) Impact of channel doping on DG-MOSFET parameters in nano regime-TCAD simulation. Int J Comput Appl 37(11):0975–8887

3. Faisal MdSA, Hasan MdR, Hossain M, Islam MS (2017) Projected performance of sub-10 nm GaN-based double-gate MOSFETs. Circ Comput Sci 2(2):15–19

4. Kaharudin KE, Salehuddin F, Zain ASM, Aziz MNIA (2016) Implementation of Taguchi method for lower drain induced barrier lowering in vertical double gate NMOS Device. J Telecommun Electron Comput Eng 8(4):11–16

5. Chiang T-K (2016) A short-channel-effect-degraded noise margin model for junctionless double-gate MOSFET working on subthreshold CMOS logic gates. IEEE Trans Electron Dev 63(8)

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