Keeper Effect on Nano Scale Silicon Domino Logic Transistors-Reference-Cited by-同舟云学术

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Keeper Effect on Nano Scale Silicon Domino Logic Transistors

Published:2021-10-14 Issue: Volume: Page:
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Pandey Amit Kumar,Gupta Tarun Kumar,Gupta Abhinav,Pandey Digvijay

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-021-01424-6.pdf

Reference29 articles.

1. Kao JT, Chandrakasan AP (2000) Dual-threshold voltage techniques for low power digital circuits. IEEE J Solid-State Circuits 35(7):1009–1018

2. Gupta TK, Khare K (2013) Lector with footed-diode inverter: A technique for leakage reduction in domino circuits. Circuits Syst Signal Process 32(6):2707–2722

3. Garg S, Gupta TK (2019) FDSTDL: Low-power technique for FinFET domino circuits. Int J Circuit Theory Appl 47(6):917–940

4. Pandey AK, Gupta TK, Verma P (2018) Sleep signal controlled footless domino circuit for low leakage current. Circuit World, Emerald Publisher 44(2):87–98

5. Gupta TK, Pandey AK, Meena OP (2017) Analysis and design of lector based dual-Vt domino logic with reduced leakage current. Circuit World, Emerald Publisher 43(3):97–104

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Effect of Noise Robustness on Domino Using Silicon Nano Materials;Silicon;2024-01-27

2. Influence of Gate Oxide and Subthreshold Leakage in Domino Using Si Nano-Materials;Silicon;2023-06-16

3. Polarization Insensitive Circular Ring Resonator Based Perfect Metamaterial Absorber Design and Simulation on a Silicon Substrate;Silicon;2022-01-20

4. Impact of Silicon Stacked Transistors on Nano Scale Domino Logic;Silicon;2022-01-06

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