Data-Driven Clock Gating for Digital Filters-Reference-Cited by-同舟云学术

Data-Driven Clock Gating for Digital Filters

Published:2010 Issue: Volume: Page:96-105
ISSN:0302-9743
Container-title:Lecture Notes in Computer Science
language:
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Author:

Bonanno Alberto,Bocca Alberto,Macii Alberto,Macii Enrico,Poncino Massimo

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/978-3-642-11802-9_14

Reference13 articles.

1. Hewlitt, R.M., Swartzlantler, E.: Canonical signed digit representation for FIR digital filters. In: 2000 IEEE Workshop on Signal Processing Systems, SiPS 2000., October 2000, pp. 416–426 (2000)

2. Freking, W.L., Parhi, K.K.: Low-power FIR digital filters using residue arithmetic. In: ASILOMAR 1997: Thirty-First Asilomar Conference on Signals, Systems & Computers, November 1997, vol. 1, pp. 739–743 (1997)

3. Sankarayya, N., Roy, K., Bhattacharya, D.: Algorithms for Low Power and high speed FIR filter realization using differential coefficients. IEEE Transactions on Circuits and Systems 44(6), 488–497 (1997)

4. Chang, T.S., Jen, C.W.: Low power FIR filter realizations with differential coefficients and inputs. In: ICASSP 2008: International Conference on Acoustics, Speech, and Signal Processing, pp. 3009–3012 (2008)

5. Ramprasad, S., Shanbhag, N.R., Hajj, I.N.: Decorrelating (DECOR) transformations for lowpower adaptive filters. In: ISLPED 1998: International Symposium on Low-Power Electronics and Design, August 1998, pp. 250–255 (1998)

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