Performance Analysis and Implementation of Array Multiplier using various Full Adder Designs for DSP Applications: A VLSI Based Approach-Reference-Cited by-同舟云学术

Performance Analysis and Implementation of Array Multiplier using various Full Adder Designs for DSP Applications: A VLSI Based Approach

Published:2016 Issue: Volume: Page:731-742
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
language:
Short-container-title:

Author:

Asha K. A.,Shinde Kunjan D.

Publisher

Springer International Publishing

Link

http://link.springer.com/content/pdf/10.1007/978-3-319-47952-1_59

Reference8 articles.

1. Kunjan D. Shinde, Jayashree C. Nidagundi, “Design of fast and efficient 1-bit full adder and its performance Analysis”, International conference on control, Instrumentation, Communication and computational technologies (ICCICCT)

2. Neha Maheshwari, “A design of 4x4 multiplier using 0.18um technology”, International Journal of Latest Trends in Engineering and Technology (IJLTET)

3. Sumit Vaidya, Deepak Dandekar, “ Delay-power performance comparison of Multipliers in VLSI circuit design”, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010

4. Elancheran.J , R.Poovendran, “ Implementation of 8T full adder in Array Multiplier”, International Journal of Advanced Technology in Engineering and Science, Volume No.03, Issue No. 03, March 2015

5. Kripa Mathew,S.Asha Latha,T.Ravi, E.Logashanmugam, “ Design and Analysis of an Array Multiplier using and Area Efficient Full adder cell in 32nm CMOS technology”, The International Journal Of Engineering And Science (Ijes) ,Volume 2 Issue 3 Pages 8-16 2013.

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Optimization of 4-Bit Array Multiplier with Adiabatic Logic Using 65 nm CMOS Technologies;IETE Journal of Research;2023-05-03

2. Power efficient multiplier using Vedic algorithm and self bias transistor technique;International Journal of Electronics;2022-11-17

3. Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology;IETE Journal of Research;2020-06-28