Power efficient multiplier using Vedic algorithm and self bias transistor technique-Reference-Cited by-同舟云学术

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Power efficient multiplier using Vedic algorithm and self bias transistor technique

Published:2022-11-17 Issue: Volume: Page:1-15
ISSN:0020-7217
Container-title:International Journal of Electronics
language:en
Short-container-title:International Journal of Electronics

Author:

Choudhary Kuldeep¹,Jadav Sunil¹,Tayal Shubham²,Kaur Preet¹,Rai Lalit¹,Sharma Rajneesh³

Affiliation:

1. Electronics Engineering Department, JC Bose University of Science & Technology YMCA, Faridabad, India

2. Electronics & Communication Engineering Department, SR University, Warangal, India

3. Electronics & Communication Engineering Department, Thapar Institute of Engineering and Technology, Patiala, India

Funder

Not Funded

Publisher

Informa UK Limited

Subject

Electrical and Electronic Engineering

Link

https://www.tandfonline.com/doi/pdf/10.1080/00207217.2022.2143575

Reference23 articles.

1. Performance Analysis and Implementation of Array Multiplier using various Full Adder Designs for DSP Applications: A VLSI Based Approach

2. Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

3. An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata

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